The present invention is directed to a system and method for conducting an accelerated soft error rate (ASER) test on semiconductor samples including integrated circuits and semiconductor devices. More particularly, the invention provides for a system and method for carrying out accelerated soft error rate tests with credibility and reliability. The invention provides for a system and method for increasing the effectiveness by which soft error rates of semiconductor devices can be modeled and enhancing by which quality control can be implemented for semiconductor devices. The invention also provides for a system and method of carrying out accelerated soft error rate tests that reduce radiation exposure to an operator of the test. Merely by way of example, the invention can be used to perform testing of BIB or DUT boards in a way compliant with JEDEC standards. Based on the number of soft errors, it may be determined as whether the semiconductor is acceptable. There are other embodiments as well. It would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
As the gate oxide gets thinner and the cell density is increased due to continuous scaling and the rapid technology advancement, however, soft error rates (SER) of semiconductor devices become an increasingly important factor to ensure device reliability. A soft error (SE) is a random error induced by an event corrupting the data stored in a device but not permanently damaging any component on the device. A soft error can be caused by particle strikes including alpha particle strikes and neutron particle strikes. As part of today's standard manufacturing process, after the individual devices have been manufactured within an IC fabrication facility, the devices must be tested and packaged to ensure the reliability of the manufactured circuits. An important test is a test characterizing the soft error rate (SER) of the manufactured devices.
While an SER is not permanent, it often defines a chip's susceptibility to error and overall reliability. In the past, tests for SER had been optional. As of now, SER tests have become a mandatory test for many processes. In addition, SER of chips is an important measure of chip quality. Therefore, it is desirable to efficiently and reliably test SER of chips, especially during the semiconductor fabrication processes.
To properly test SER of chips, it is often necessary to simulate to conditions that cause SE on semiconductor chips or devices. One of the common causes of SE is particle strikes. Newer semiconductor chips are becoming increasingly susceptible to SE caused by particle strikes because of the increasing applications of integrated circuits in space where a lot more cosmic rays and particle strikes are expected. Conditions such as cosmic rays usually take effect over time. To speedily test SER of chips, the accelerated soft-error rate (ASER) is often determined, and it is measured by failure-in-time (FIT).
Soft errors can be caused by single-event upsets (SEU's), random, isolated events caused by passage of cosmic rays or transient ionizing particles such as alpha particles. A stray ionizing particles, for example, can generate enough free charge to flip a structure or device to its opposite state, thereby corrupting the operations of a device. In an integrated circuit (IC) chip package, emission of trace amounts of radioactive impurities is one cause of SEU's.
Accelerated soft-error rate (ASER) tests are a practical way of characterizing a semiconductor device's robustness to soft errors in an accelerated and shortened period. A typical ASER test measures a semiconductor device in terms of FIT (Failure In Time) given a known quantity of radiation source. In a typical ASER test, a radiation source is placed near a semiconductor device to be tested. Testing equipments are then attached to burn-in-boards (BIBs) or device-under-test (DUT) boards to record the failure in time the radiation source causes on the semiconductor being tested.
Accurate estimates of soft error rates (SER's) in electronic systems due to radiation exposure are desirable for the implementation of reliable systems. Examples of radiation sources include alpha particle sources with a known emission rate, such as, for example, a thorium foil. According to an embodiment, DUT boards include printed circuit boards that interface between a semiconductor device to be tested (e.g., an integrated circuit) and a test head attached to an automatic test equipment (ATE). DUT boards may be used to test individual chips of silicon wafers before they are cut free and packaged or to test packaged IC's.
In specialized applications such as space applications, soft error test is even important due to exposure from space radiation encountered in outer space. But in general, even in down-to-earth applications, concerns about soft error rates arising from high density devices means that tests of soft error rates are becoming mandatory in increasingly more and more applications. In many applications, for example, it is a challenge to maintain the common industrial standard for ASER, 1,000-FIT, on a 0.1 um or sub 0.1 um technology platform.
A problem with standard ASER tests is the sensitivity the test results depend on the parameters of a test. ASER tests are often conducted by skilled technicians trained to hold a well-characterized sample of radiation source at a distance from a DUT board. The specific distance and orientation at which the technician hold the radiation from the DUT board affect the radiation exposure of the semiconductor device and may thus drastically affect the ASER FIT measurements taken. A consequence is that test results are often sensitive to the technicians conducting the tests and are difficult to produce with high credibility or reliability.
Another problem with standard ASER tests is the risk technicians are subjected to harmful radiation exposure. While trained technicians usually handle radiation sources with protective gear, the close proximity by which technicians handle the radiation sources means that technicians can accidentally be subjected to unhealthful doses of harmful radiation in their daily routine. From the above, it can be seen that an improved technique for conducting ASER tests is desired.